Reduceron - a functional CPU

The Reduceron is a configurable hardware processor (FPGA) that runs functional languages extremely efficiently, with most reduction steps taking a single clock cycle or less.

You find two scientific papers about it here

And here a maintained implementation plus a couple of other papers:

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Found another one

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Wow! This is an insanely good idea :smiley: .

I’ll read the papers as soon as time permits.

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All but the jpf article is part of the repository. Note, the two papers describe two different iterations of the design.

All of the software (except the GHC front end) works, but it’s not currently useful for practical problems (hint, help welcome).

Note also, Reduceron is designed for lazy evaluation, though most of the ideas would benefit a strict language as well.

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